72022-01-13 09:32:31danger@telecom-paristech.fr62022-01-13 09:31:57danger@telecom-paristech.fr52021-03-04 10:08:25David NovoAdded reference on gem5 calibration of a Cortex A53 CPU42020-02-12 16:33:49danger@telecom-paristech.fr32020-02-12 16:32:50danger@telecom-paristech.fr22020-02-12 16:31:54danger@telecom-paristech.fr12020-02-12 16:31:29danger@telecom-paristech.frPage des publications utiles pour ARCHISEC

gem5 tutorial.pdf. 2017. Architectures. 2018. . 2018. . 2018. ARM, Cortex A9 MPCore Accelerator Coherency Port. Accessed: 2017-04-12. ARM

Q. Huppert, T. Evenblij, M. Perumkunnil, F. Catthoor, L. Torres, and D. Novo. "Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation." In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE) 2021. Bossuet, L. (2018, December). Dvfs as a security failure of trustzone-enabled heterogeneous soc. In 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (pp. 489-492). IEEE.